Huawei has unveiled significant advancements in chip design with the updated "Tao's Law" paper, version 2.0, detailing the "LogicFolding" process parameters. The new iteration, released by Huawei board member and semiconductor business president He Tingbo on the Chinese Academy of Sciences ChinaXiv platform, reveals that the Kirin 2026 chip achieves a 41% power reduction at equivalent performance levels. This development comes just 39 days after the initial V1 presentation at the 2026 International Symposium on Circuits and Systems in Shanghai.
The V2 paper highlights that the Kirin 2026, fabricated on the same process node as its predecessor, the Kirin 9030 Pro, operates at 0.9V compared to 1.1V. This architectural change, driven by LogicFolding, also results in a 37.5% die area reduction and 5.6% lower power density, all without relying on new lithography technology. According to the Economic Observer, these gains are entirely attributed to innovative architectural changes.
For the first time, the updated paper provides critical details on LogicFolding process parameters, including a key metric called "gear ratio." This ratio measures the relationship between hybrid bonding interconnect pitch and top metal layer routing pitch, with lower ratios enabling more optimized circuit unit levels. The Kirin 2026 currently utilizes a 1.5-micron hybrid bonding pitch, with a future target of sub-1-micron pitch and an overlay accuracy within 0.5 microns.
Huawei opted for wafer-to-wafer hybrid bonding over sequential 3D integration to avoid potential performance degradation in bottom-layer devices caused by high-temperature processing. The company's roadmap outlines ambitious targets through 2031, with the Kirin 2026 and 2027 chips already taped out, and the Kirin 2028 and 2029 in pre-tapeout stages. CPU clock frequencies have seen a substantial jump from 2.75GHz on the 9030 Pro to 3.1GHz on the Kirin 2026, marking a 12% single-generation gain.
The roadmap projects CPU clock frequencies to reach 4.3GHz by 2030 with a transistor density of 292 MTr/mm², and an impressive 5GHz by 2031, exceeding 400 MTr/mm²—a density equivalent to a 1.4nm process level. These advancements underscore Huawei's strategic focus on enhancing chip performance and efficiency through innovative design and integration techniques.
